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215
PRELIMINARY
CY2215
133-MHz Spread Spectrum Frequency Timing Generator
Features * Mixed 2.5V and 3.3V Operation * Multiple output clocks at different frequencies -- Three CPU clocks, up to 133 MHz -- Ten synchronous PCI clocks, 1 free-running -- One CPU/2 clock, at one-half the CPU frequency -- Three 66 MHz clocks -- One synchronous IOAPIC clock, at 16.67 MHz -- One 48 MHz clock -- Two reference clocks at 14.318 MHz * Spread Spectrum clocking -- 31 kHz modulation frequency -- EPROM programmable percentage of spreading. Default is -0.5%, which is recommended by Intel(R). * Power-down features * Three Select inputs * Low skew and low jitter outputs * OE and Test Mode support * 48-pin SSOP package Benefits Usable with Pentium II, K6, and 6x86 Processors Single chip main motherboard clock generator -- Driven together, support 3 CPUs and a chipset -- Support for 4 PCI slots and chipset -- Drives up to two main memory clock generators, including DRCG -- Support for multiple AGP slots -- Support multiprocessing systems -- Supports USB frequencies and I/O chip -- Supports ISA slots and I/O chip Enables reduction of EMI in some systems
Supports mobile systems Supports up to eight CPU clock frequencies Meet tight system timing requirements at high frequency Enables ATE and "bed of nails" testing Widely available, standard package enables lower cost
Logic Block Diagram
SEL0 REFCLK0 (14.318 MHz) REFCLK1 (14.318 MHz) CPUCLK [0-2]
SEL0/REFCLK0 REFCLK1 VDDREF XTALIN XTALOUT VSSPCI PCICLK_F
SSOP Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSSREF VDDAPIC IOAPIC VSSAPIC VDDCPU/2 CPUCLK/2 VSSCPU/2 VDDCPU CPUCLK2 VSSCPU VDDCPU CPUCLK1 CPUCLK0 VSSCPU AVDD AVSS PWR_DWN SPREAD SEL1 NC VDD48 48CLK VSS48 SEL133
XTALIN
XTALOUT
14.318 MHz OSC.
CPU PLL
SEL1 SEL133 SPREAD
EPROM
PCICLK4
PCICLK [1-9] (33.33 MHz) IOAPIC (16.67 MHz) 66CLK [0-2] (66.67 MHz)
PCICLK5 VSSPCI PCICLK6 PCICLK7 VDDPCI PCICLK8 PCICLK9 VSS66 66CLK0 66CLK1 66CLK2 VDD66
PWR_DWN
SYS PLL
48 MHz CLK
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
CY2215-1 *
Divider, EPROM-Prog Delay and Stop Logic
CPUCLK/2 PCICLK_F (33.33 MHz)
PCICLK1 VDDPCI PCICLK2 PCICLK3
408-943-2600 October 1, 1999
PRELIMINARY
Pin Summary
Name VSSREF VDDREF VSSPCI VDDPCI VSS66 VDD66 VSS48 VDD48 VSSCPU VDDCPU VSSCPU/2 VDDCPU/2 VSSAPIC VDDAPIC AVDD AVSS XTALIN[1] XTALOUT
[1]
CY2215
Pins 48 3 6, 14 9, 17 20 24 26 28 35, 39 38, 41 42 44 45 47 34 33 4 5 36, 37, 40 8, 10, 11, 12, 13, 15, 16, 18, 19 7 43 21, 22, 23 46 1,2 27 32 31 30 1 25 29
Description 3.3V Reference ground 3.3V Reference voltage supply 3.3V PCI ground 3.3V PCI voltage supply 3.3V 66 MHz ground 3.3V 66 MHz voltage supply 3.3V 48 MHz ground 3.3V 48 MHz voltage supply 2.5V CPU ground 2.5V CPU voltage supply 2.5V CPU/2 ground 2.5V CPU/2 voltage supply 2.5V IOAPIC ground 2.5V IOAPIC voltage supply Analog voltage supply to PLL and Core Analog ground Reference crystal input Reference crystal feedback CPU clock outputs PCI clock outputs, synchronously running at 33.33 MHz Free running PCI clock CPU/2 clock outputs, drive memory clock generator 66.67 MHz clock outputs IOAPIC clock output, running at 16.67 MHz Reference clock outputs, 14.318 MHz 48 MHz clock output Active LOW input, powers down part when asserted Active LOW input, enables spread spectrum when asserted CPU frequency select input (See Function Table) CPU frequency select input (See Function Table). Internal 50K pull-up CPU frequency select input (See Function Table) No Connect Pin, no internal connection
CPUCLK [0-2] PCICLK [1-9] PCICLK_F CPUCLK/2 66CLK [0-2] IOAPIC REFCLK [0-1] 48CLK PWR_DWN SPREAD SEL1 SEL0[2] SEL133 NC
Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, "Crystal Oscillator Topics." 2. Pin 1, SEL0 Function, is only active at power-on.
2
PRELIMINARY
Function Table
SEL133 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 SEL1 0 1 0 1 0 1 0 1 SEL0 CPUCLK (MHz) Hi-Z N/A 100 100 TCLK/2 N/A 133.33 133.33 CPUCLK/2 (MHz) Hi-Z N/A 50 50 TCLK/4 N/A 66.67 66.67 66CLK (MHz) Hi-Z N/A 66.67 66.67 TCLK/4 N/A 66.67 66.67 PCICLK (MHz) Hi-Z N/A 33.33 33.33 TCLK/8 N/A 33.33 33.33 48CLK (MHz) Hi-Z N/A OFF 48 TCLK/2 N/A OFF 48 REFCLK (MHz) Hi-Z N/A 14.318 14.318 TCLK N/A 14.318 14.318
CY2215
IOAPIC (MHz) Hi-Z N/A 16.67 16.67 TCLK/16 N/A 16.67 16.67
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK 48CLK Target Frequency (MHz) 100.0 133.33 48.0 Actual Frequency (MHz) TBD TBD 48.008 PPM TBD TBD 167
Clock Enable Configuration
PWR_DWN 0 1 All Clocks LOW ON OSC. OFF ON VCOs OFF ON
Clock Driver Impedances
Impedance Buffer Name CPU, CPU/2, IOAPIC 48CLK, REF PCI, 66CLK VDD Range 2.375 - 2.625 3.135 - 3.465 3.135 - 3.465 Buffer Type Type 1 Type 3 Type 5 Minimum 13.5 20 12 Typical 29 40 30 Maximum 45 60 55
Note: 3. TCLK is a test clock driven in on the XTALIN input in test mode.
3
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5
CY2215
Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions Over which Electrical Parameters are Guaranteed
Parameter VDDREF, VDDPCI, AVDD, VDD66, VDD4848CLK VDDCPU, VDDCPU/2 VDDAPIC TA CL Description 3.3V Supply Voltages CPU and CPU/2 Supply Voltage IOAPIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, CPUCLK/2, 48CLK, REF PCICLK, 66CLK, IOAPIC Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.375 2.375 0 Max. 3.465 2.625 2.625 70 20 30 14.318 MHz Unit V V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage Input High Current Input Low Current High-level Output Current Except Crystal Pads 0 < VIN < VDD 0 < VIN < VDD CPU, CPU/2, IOAPIC 48CLK, REF 66CLK, PCI IOL Low-level Output Current CPU, CPU/2, IOAPIC 48CLK, REF 66CLK, PCI IOZ IOZ IDD2 IDD3 IDDPD2 IDDPD3 Output Leakage Current Output Leakage Current Three-state, excluding REF0 Three-state, REF0 Type 1, VOH = 2.375V Type 3, VOH = 3.135V Type 5, VOH = 3.135V Type 1, VOL = 0.3V Type 3, VOL = 0.4V Type 5, VOL = 0.4V Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 10 10 -27 -23 -33 30 27 38 10 150 50 150 100 200 A pA mA mA A A mA V V A A mA
2.5V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz 3.3V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz 2.5V Shutdown Current 3.3V Shutdown Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V AVDD/VDDQ3 = 3.465V, V DD25 = 2.625V
4
PRELIMINARY
CY2215 Switching Characteristics[4] Over the Operating Range
Parameter t1 t2 t2 t2 t3 t3 t3 t6 t9 t10 t11 t12 t13 All CPU, CPU/2, IOAPIC 48CLK, REF PCI, 66CLK CPU, CPU/2, IOAPIC 48CLK, REF PCI, 66CLK CPU 66CLK PCI CPU, 66CLK 66CLK, PCI CPU, IOAPIC CPU CPU CPU/2 IOAPIC 48CLK 66CLK REF CPU, PCI Output Description Output Duty Cycle Rising Edge Rate Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate Falling Edge Rate CPU-CPU Skew 66CLK-66CLK Skew PCI-PCI Skew CPU-66CLK Clock Skew 66CLK-PCI Clock Skew IOAPIC-CPU Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Settle Time CPU and PCI clock stabilization from power-up
[5]
CY2215
Test Conditions t1A/(t1A + t1B) Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 2.0V and 0.4V Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.25V Measured at 1.5V Measured at 1.5V CPU leads. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks 66CLK leads. Measured at 1.5V APIC leads. Measured at 1.25V With all outputs running With the 48CLK output turned off
Min. 45 1.0 0.5 1.0 1.0 0.5 1.0
Max. 55 4.0 2.0 4.0 4.0 2.0 4.0 175 250 500
Unit % V/ns V/ns V/ns V/ns V/ns V/ns ps ps ps ns ns ns ps ps ps ps ps ps ps ms
0 1.5 1.5
1.5 4.0 4 250 200 250 500 500 500 1000 3
Notes: 4. All parameters specified with fully loaded outputs with the exception of PCI outputs where the sum of all loads on the pci outputs are not to exceed 240pf and AGP outputs should not exceed 75 pF total lump load. 5. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
5
PRELIMINARY
Switching Waveforms
Duty Cycle Timing
t1A t1B
CY2215
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3
CPU-CPU Clock Skew
CPUCLK
CPUCLK t6
66CLK-66CLK Clock Skew
66CLK
66CLK t9
PCI-PCI Clock Skew
PCI
PCI t10
6
PRELIMINARY
Switching Waveforms (continued)
CPU-66CLK Clock Skew
CPU
CY2215
66CLK t11
66CLK-PCI Clock Skew
66CLK
PCI t12
CPU-IOAPIC Clock Skew
CPU t13
IOAPIC
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Note: 6. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
7
PRELIMINARY
Test Circuit
VDDPCI, VDD66, VDD48, VDDREF, AVDD
CY2215
6, 14, 20, 26, 33, 35, 39, 42, 45, 48 3, 9, 17, 24, 28, 34 CY2215
VDDCPU, VDDCPU/2, VDDAPIC 38, 41, 44, 47
OUTPUTS CLOAD
Note: Each supply pin must have an individual decoupling capacitor. Note: All Capacitors must be placed as close to the pins as is physically possible.
Ordering Information
Ordering Code CY2215PVC-1 Document #: 38-00772 Package Name O48 Package Type 48-Pin SSOP Operating Range Commercial
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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